1. Field of the Disclosure
The present disclosure relates to a phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit, and more particularly, to a PLL circuit for reducing frequency lock time and improving operational characteristics, and further relates to an associated method for reducing frequency lock time for PLL circuits.
2. Description of Related Art
A phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit is a circuit for comparing the phase of a reference clock signal with the phase of a signal fed back from a voltage controlled oscillator (xe2x80x9cVCOxe2x80x9d), and synchronizing the two phases. A PLL circuit is used in various fields, such as, for example, in communication systems.
As shown in FIG. 1, a PLL circuit includes a phase detector 11 for comparing the phase of a reference clock signal fr with the phase of a feedback clock signal fv and detecting a phase difference, a loop filter 13, a VCO 15 for generating an output clock signal of and varying the frequency of the output clock signal of in response to an output voltage Vc of the loop filter 13, and a divider 17 for dividing the output clock signal of at a predetermined division rate N and supplying the divided clock signal as a feedback clock signal fv.
A method for reducing frequency lock time in the PLL circuit of FIG. 1 might be to control some loop parameters and to vary a loop bandwidth. However, this method has disadvantages including that it cannot reduce frequency lock time sufficiently.
These and other drawbacks and disadvantages are addressed by a phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit having a phase detector for comparing the phase of a reference clock signal with the phase of a feedback clock signal and detecting a phase difference between the two; a loop filter in signal communication with the phase detector; a fast frequency lock control circuit in signal communication with the phase detector for disconnecting the phase detector from the loop filter at the initial stage of power on of the phase-locked loop circuit, at least one of supplying constant current to the loop filter for a predetermined time duration and emitting constant current from the loop filter, and then connecting the phase detector to the loop filter; a voltage controlled oscillator in signal communication with the loop filter for generating an output clock signal and varying the frequency of the output clock signal in response to output voltage of the loop filter; and a divider in signal communication with the voltage controlled oscillator for dividing the output clock signal at a predetermined division rate and supplying the divided clock signal as the feedback clock signal.
In operation, the phase detector compares the phase of a reference clock signal with the phase of a feedback clock signal and detects a phase difference. The fast frequency lock control circuit disconnects the phase detector from the loop filter at the initial stage of power on of the PLL circuit and supplies constant current to the loop filter for a predetermined time duration, or emits constant current from the loop filter and then connecting the phase detector to the loop filter. The voltage-controlled oscillator generates an output clock signal and varies the frequency of the output clock signal in response to output voltage of the loop filter. The divider divides the output clock signal at a predetermined division rate and supplies the divided clock signal as the feedback clock signal.
According to a preferred embodiment, the fast frequency lock control circuit includes a constant current source, one end of which is maintained at a first reference voltage, a first switch connected between the other end of the constant current source and the loop filter, a second switch connected between the phase detector and the loop filter, and a control circuit for turning on the first switch and turning off the second switch for the predetermined time duration, and for turning off the first switch and turning on the second switch after the predetermined time duration, in response to input data and a control clock signal.
A preferred feature is that the input data be the division rate of the divider, and that the control clock signal be the same as the reference clock signal. Another preferred feature is that the control circuit be implemented by a lock-detecting counter included in the PLL circuit, and that the constant current source be implemented by a charge pump included in the phase detector.
According to another preferred embodiment, the fast frequency lock control circuit includes a first constant current source, one end of which is maintained at a first reference voltage, a first switch connected between the other end of the first constant current source and the loop filter, a second switch connected between the phase detector and the loop filter, a second constant current source, one end of which is maintained at a second reference voltage, a third switch connected between the other end of the second constant current source and the loop filter, a fourth switch connected between the loop filter and the voltage controlled oscillator, and a control circuit for turning on one of the first switch and the third switch and turning off the second switch and the fourth switch for the predetermined time duration, and for turning off the first switch and the third switch and turning on the second switch and the fourth switch after the predetermined time duration, in response to input data and a control clock signal.
A preferred feature is that the input data is the division rate of the divider, and the control clock signal is the same as the reference clock signal. Another preferred feature is that the control circuit be implemented by a lock detecting counter included in the PLL circuit, and that the first constant current source and the second constant current source be implemented by a charge pump included in the phase detector.
A method for reducing frequency lock time of a phase-locked loop circuit includes the steps of disconnecting the phase detector from the loop filter at the initial stage of power on of the PLL circuit and supplying constant current to the loop filter for a predetermined time duration, or emitting constant current from the loop filter, and connecting the phase detector to the loop filter after the predetermined time duration.
According to another preferred embodiment, the step of supplying the constant current to the loop filter includes the steps of generating the constant current, and connecting a path of the constant current to the loop filter and disconnecting the phase detector from the loop filter for the predetermined time duration in response to input data and a control clock signal. A preferred feature is that the input data be the division rate of the divider, and that the control clock signal be the same as the reference clock signal.